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Including a Low-pass Filter to an ADC Mannequin and DAC Modeling – Technical Articles

We conclude our sequence by discussing a proposed mannequin for ADC simulation.

You’ll be able to catch up the dialog with the next hyperlinks:

Please recall {that a} full listing of abbreviations, glossaries, and a whole listing of references may be present in the first article of the series.

 

A Proposal for an Even Higher ADC Mannequin

A two-tone check sign offers extra details about ADC efficiency than a one-tone. Your writer’s mannequin offers a great match to the producer’s mannequin for a specific ADC so bit error fee simulations may very well be run conveniently. This ADC occurred to have a really huge enter bandwidth.

For ADC with decrease bandwidths, the addition of a low-pass filter as proven in Determine 1 would give a greater mannequin.

 

Determine 1. An improved ADC mannequin based mostly on the previous article

 

Additionally, as mentioned within the first part of our previous article, an improved mannequin would enable as much as 6 dB of additive white Gaussian noise to be added, to present a greater match to the actual ADC’s noise ground.

The producer’s mannequin was a “behavioral”, not an actual mannequin. It will be good to do the identical comparability towards an in depth SPICE mannequin, or measurements on an precise bodily gadget.

 

Fashions for Digital-to-Analog Converters (DACs)

References [19] via [26] current some type of DAC mannequin, while [27] via [29] describe traits of DACs, however not fashions. Of these presenting fashions most ([19], [20], [22], and [23]) current fashions that appear of curiosity to DAC designers, not customers, giving detailed particular fashions to find out issues like SNR, or the impact of clock jitter on the output spectrum.

Others current fashions which appear too easy. These are [25], which solely takes under consideration clipping with out quantization; and [26], which fashions quantization and clipping as additive processes, which is simply legitimate for Gaussian inputs.

Reference [21] fashions the DAC output (y(t)) as a perform of the DAC enter (x(t)), utilizing the equation:

 

y(t) = x(t) + yHQ(x(t))  +  yCM(x(t))  + yVQ(x(t))

Equation 1

 

the place these are the corresponding phrases: 

  • yHQ(x(t)) accounts for “horizontal quantization” (best time sampling)
  • yCM(x(t)) accounts for “clock supply modulation” (clock jitter)
  • yVQ(x(t)) accounts for “vertical quantization” (amplitude quantization) together with integral non-linearity. 

The expressions for these phrases aren’t extraordinarily sophisticated, so this may make a great mannequin for simulation of DACs. The enter, x(t), may be from a floating-point implementation of the modulation algorithm, or from a set level one with output M bits, the place M > NE; the place NE is the variety of efficient bits of the DAC.

Reference [24] presents a mannequin which takes under consideration differential non-linearity (DNL), integral non-linearity (INL), achieve and offset errors, glitch impulse space, and settling time.

Determine 5 of [24] reveals a block diagram of the mannequin. It consists of additive random errors to mannequin DNL; additions of deterministic features of time to mannequin glitches; a polynomial perform to mannequin INL, achieve and offset errors; a delay and time slew (which isn’t defined within the textual content); a low-pass filter to mannequin settling time; and a noise mannequin (additionally not defined within the textual content). Determine 5 from [24] may very well be modified some, producing Determine 2 right here, which is the inverse of the ADC mannequin in Determine 1; with the addition of additive noise accessible if the output noise as a result of quantization will not be sufficient.

 

Determine 2. A modification of a DAC mannequin from Naoues, M.; Morche, D.; Dehos, C.; Barrak, R.; and Ghazel, A, [24]

 

The reader may marvel why, for the reason that enter to the DAC is already digital, the sampler and quantizer in Determine 2 are wanted.

Usually, for simulation, a continuous-time, floating level, algorithm is on the market; and it’s not definitely worth the expense to transform it to a clocked, fixed-point model. (Steady-time means the simulation sampling frequency is excessive sufficient so there aren’t any sampling results.) Additionally, usually the precise variety of bits accessible on the DAC interface (the marketed variety of bits) is bigger than the ENOB.

 


 

What extra questions do you’ve gotten about modeling ADCs (and DACs) for system simulation? Share your ideas within the feedback beneath.

 

References

DAC Evaluation, Fashions, Simulation, Testing, and Specs

[19] Wikner, J.J.; Nianxiang Tan, “Modeling of CMOS digital-to-analog converters for telecommunication,” Circuits and Programs II: Analog and Digital Sign Processing, IEEE Transactions on , vol.46, no.5, pp.489,499, Could 1999

[20] Angrisani, L.; D’Arco, M., “Modeling Timing Jitter Results in Digital-to-Analog Converters,” Instrumentation and Measurement, IEEE Transactions on, vol.58, no.2, pp.330,336, Feb. 2009

[21] D’Apuzzo, M.; D’Arco, M.; Liccardo, A; Vadursi, M., “Modeling DAC Output Waveforms,” Instrumentation and Measurement, IEEE Transactions on, vol.59, no.11, pp.2854,2862, Nov. 2010

[22] Myderrizi, I; Zeki, A, “Present-Steering Digital-to-Analog Converters: Purposeful Specs, Design Fundamentals, and Behavioral Modeling,” Antennas and Propagation Journal, IEEE, vol.52, no.4, pp.197,208, Aug. 2010

[23] Sang Min Lee; Taleie, S.M.; Saripalli, G.R.; Dongwon Website positioning, “Clock-Part-Noise-Induced TX Leakage Estimation of a Baseband Wi-fi Transmitter DAC,” Circuits and Programs II: Categorical Briefs, IEEE Transactions on , vol.59, no.5, pp.277,281, Could 2012

[24] Naoues, M.; Morche, D.; Dehos, C.; Barrak, R.; Ghazel, A, “Novel behavioral DAC modeling approach for WirelessHD system specification,” Electronics, Circuits, and Programs, 2009. ICECS 2009. sixteenth IEEE Worldwide Convention on, vol., no., pp.543,546, 13-16 Dec. 2009

[25] Kitaek Bae; Changyong Shin; Powers, E.J., “Efficiency Evaluation of OFDM Programs with Chosen Mapping within the Presence of Nonlinearity,” Wi-fi Communications, IEEE Transactions on , vol.12, no.5, pp.2314,2322, Could 2013

[26] Ling, W.A, “Shaping Quantization Noise and Clipping Distortion in Direct-Detection Discrete Multitone,” Lightwave Know-how, Journal of, vol.32, no.9, pp.1750,1758, May1, 2014

[27] Engel, G.; Fague, D.E.; Toledano, A, “RF digital-to-analog converters allow direct synthesis of communications alerts,” Communications Journal, IEEE, vol.50, no.10, pp.108,116, October 2012

[28] Pearson, Chris; “Excessive Velocity, Digital to Analog Converters Fundamentals”; Texas Devices Software Report SLAA523A; 2012

[29] Munson, Justin; “Understanding Excessive Velocity DAC Testing and Analysis”; Analog Units Software Word AN-928; 2013

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